This invention relates to digital data communication in general, and more particularly to methods and apparatus for regenerating clock signal embedded in a synchronous digital data stream. The invention is generally applicable to the synchronization of digital symbols containing multiple bits. A proposed application of the invention is in a Maximum Likelihood Detector (MLD) wherein digital symbols are recovered and reconstructed. In a common application, the invention is applicable primarily to a binary-level digital data stream.
An important function in a communications system is the reconstruction or regeneration of the embedded clock signal from a received signal comprising a digital data stream of binary or multiple-bit symbols. The regenerated clock is used to decode the information contained within the digital data stream.
There are however many sources of error which can result in degraded synchronization of the clock signal and the accompanying data.
In the past, techniques used to sample digital bit streams have been based on considerable a priori information about the nature of the received data. A conventional UART (Universal Asynchronous Receiver Transmitter) includes the capability to sample a binary digital bit stream at a fixed offset from a leading edge of a start bit and all subsequent bits in the data unit (word). A conventional UART assumes that the source clock and the target clock are close enough in frequency that phase shift does not exceed a significant fraction of a bit in ten bits of information. This assumption, however, gives rises to problems in that slicing levels, that is, the conversion point between continuous analog levels and two digital levels, may be incorrectly set. This will cause an apparent bit width of one-type bits to differ from the apparent bit width of zero-type bits. The ideal sampling point is conventionally believed to be the center of any bit width. Because of the slicing errors, which cause a fixed offset from the leading edge of a start bit, conventional UART technology does not guarantee the sampling point to occur at the center of the bit. Hence, the sampling point does not normally occur where the signal-to-noise ratio is largest, the point of the least likelihood of error.
If the transmitting and receiving clocks are not closely synchronized in frequency, the sampling point can drift rapidly from the original position. As a consequence, the message length of any bit stream is limited by the relative phase coherence of the two clocks. Conventionally, the message length is limited to around ten bits to allow resynchronization of the clock edge after a preceding stop bit and on a subsequent start bit.
In a prior co-pending patent application, Ser. No. 07/317,213 filed Feb. 28, 1989, entitled: "Modulation and Demodulation System Employing AM-PSK and QPSK for Communications System Using Digital Signals" in the names of Robert P. McNamara, Timothy P. Murphy and James C. Long, there is described a method for synchronizing a transmit clock with a central receive clock which addresses the clock rate slip problem. In that method, only the phase of the error remained an unknown. Bit width variation caused by slicing level errors as described above was addressed and solved by measuring the width of a one-type bit so that the time relation between the rising edge and the falling edge could be used in the decision process for synchronization.
While the above method represents an improvement over the prior art, it is subject to a number of limitations. Due to the nature of the sampling process, the actual data edges can occur up to one sampling period earlier than indicated by the sampling output. As a consequence, the average error is one-half sample period late. There are other limitations which give an incorrect idea of the timing of the data edges. For example, if the sampling occurs near an edge (a transition point), noise may cause up to one sampling period of error on each edge. This gives rise to a potential maximum sampling error of one sampling period.
Round-off errors occur where the calculated bit width is an odd number of sample periods and division by two is used to find the center of the bit period. This is an error which can add up to one-half sampling period error in either direction.
In the foregoing method, only the one-type transitions are sampled and measured in order to find the center of a bit period. As a consequence, only half the number of available tries are used to find a correct sample point, since the preamble in a synchronous bit stream is alternating one's and zero's.
In the foregoing method, a timer is used to determine the end of a preamble. This requires a safety margin such that fewer bits than the number available are used to find the correct sample point in order to avoid measuring bits not in the preamble.
What is needed is a mechanism to address and minimize the likelihood of phase error and the resulting regenerated symbol value error as a result of symbol synchronization operations.